The present invention relates generally to integrated circuits. More specifically, the present invention relates to microcontrollers that are capable of interfacing with an external device, such as memory devices and multi-functional peripheral devices.
Over the years, various microcontrollers have been developed for various applications. Presently, many microcontrollers are designed to interface with a single type of external memory device, such as a particular type of SRAM or DRAM or a multi-functional peripheral. Additionally, microcontrollers are typically designed to interface with a specific subtype of external device (e.g., different SRAM subtypes having different interface requirements). By way of example, a microcontroller typically includes capabilities for interfacing with either an SRAM configured to receive separate read and write enable signals, an SRAM configured to receive a combined read and write enable signal, or an SRAM configured to receive a read enable signal and more than one write enable signal.
FIG. 1A is a diagrammatic representation of an external device 100 of a first subtype (Type I) and associated I/O pins. Motorola's MCM6323, 64Kx16 Bit, 3.3 V, Asynchronous Fast Static RAM is an example of a Type I external device, a specification of which is included in Appendix A as Item 1 (incorporated herein by reference in its entirety). As shown, the Type I external device 100 is configured to receive a plurality of address (ADR) signals, a plurality of data signals (DB), a chip select (CS!) signal, a read (RD!) enable signal, a write (WR!) enable signal, a byte enable low (BEL!) signal, and a byte enable high (BEH!) signal. (An "!" denotes that the signal is enabled at a low state). The BEL! and BEH! are optional, and some Type I external devices do not include such inputs.
These signals that are received by the external device 100 provide many functions that are required for accessing memory within the external device 100. The CS! signal is required to enable and initiate access to the external device 100. The RD! signal is needed to enable and initiate a read from the external device 100, and the WR! signal is needed to enable and initiate a write to the external device 100. When a RD! signal is provided to the external device that indicates a read operation is to be performed, the external device 100 outputs data onto the DB. Specifically, the data is output from a memory location within the external device 100 that is specified by the received ADR signals. Conversely, when a WR! is provided that indicates a write operation is to be performed, the external device 100 receives data via the DB into the specified memory location. The BEL! and BEH! are optional, and some Type I external devices do not include such inputs. Additionally, some Type I external devices include more than one pair of byte enable signals.
FIG. 1B are typical timing diagrams for I/O signals that are required as input into the Type I external device 100 of FIG. 1A to enable a read operation. As shown, the timing diagrams include a plurality of address (ADR) signals, a chip select (CS!) signal, a read (RD!) enable signal, a write (WR!) enable signal, a byte enable low (BEL!) signal, and a byte enable high (BEH!) signal. As shown, the ADR signals transition from a first value 102 to a second value 106 during period 104. The CS! signal transitions from a high value 108 to a low value 112 during a portion of the second ADR value. When the CS! signal is at a low value, access to the external device 100 is enabled. After the external device 100 is enabled, the RD! signal transitions from a high value 114 to a low value 118 to enable a read operation. The WR! signal remains at a high value 120 such that a write operation is not enabled.
Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state 122 to a low state 124 to enable the read operation only for certain bytes of data. For example, if the BEL signal remains high and the BEH signal transitions to a low value, data is read only from an upper byte of the specified memory location and not from the lower byte. That is, only the output drivers of the enabled bytes are activated within the external device 100.
FIG. 1C are typical timing diagrams for I/O signals that are required as input into the external device 100 of FIG. 1A to enable a write operation. As shown, the I/O signals for a write operation are similar to the I/O signals for a read operation. However, the WR! signals transitions from a high value 166 to a low value 170 to enable the write operation, and the RD! signal remains at a high state 164.
Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state 172 to a low state 176 to enable the write operation only for certain bytes of data. For example, if the BEL signal remains high and the BEH signal transitions to a low value, data is written only into an upper byte of the specified memory location and not into the lower byte.
FIG. 2A is a diagrammatic representation of an external device 200 of a second subtype (Type II) and associated I/O pins. Motorolla's MC68HC901 Multi-Function Peripheral is an example of a Type II external device, a specification of which is included in Appendix A as Item 2 (incorporated herein by reference in its entirety). As shown, Type II is configured to receive a plurality of address (ADR) signals, a plurality of data signals (DB), a chip select (CS!) signal, a combined read and write (RD/WR!) enable signal, a byte enable low (BEL!) signal, and a byte enable high (BEH!) signal.
The BEL! and BEH! are merely illustrative, and some external devices may have a different number of byte enable inputs. For example, some external devices (e.g., a 32 bit external device) require more than one pair of byte enable signals, while other external devices (e.g., an 8 bit external device) only require a single byte enable (or data enable) signal.
The Type II device has different read and write mechanisms than the Type I external device. The Type II device requires a combined read and write enable (RD/WR!) signal, while the Type I device requires separate read and write enable (RD! and WR!) signals.
FIG. 2B are typical timing diagrams for I/O signals that are required as input into the external device of FIG. 2A to enable a read operation. As shown, the CS! signal transitions from a high state 208 to a low state 212 to enable access to the Type II external device. Additionally, the RD/WR! signal remains at a high value 214 to enable the read operation. Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state 216 to a low state 218 to enable the read operation only for the indicated bytes(s).
FIG. 2C are typical timing diagrams for I/O signals that are required as input into the external device of FIG. 2A to enable a write operation. As shown, the I/O signals for a write operation are similar to the I/O signals for a read operation. However, the RD/WR! transitions from a high state 264 to a low state 267 to enable a write operation. Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state 266 to a low state 270 to enable the write operation only for the indicated bytes(s).
FIG. 3A is a diagrammatic representation of an external device 300 of a third subtype (Type III) and associated I/O pins. Cypress' CYM1838, 128Kx32 Static RAM Module is an example of a Type III external device, a specification of which is included in Appendix A as Item 3 (incorporated herein by reference in its entirety). As shown, Type III is configured to receive a plurality of address (ADR) signals, a plurality of data signals (DB), a chip select (CS!) signal, a read (RD!) enable signal, a write enable low (WEL!) signal, and a write enable high (WEH!) signal. Some Type III external devices include more than one pair of write enable signals.
The Type III device has different read and write mechanisms than the Type I and Type II external devices. The Type III device requires a RD! signal to enable a read instruction, and separate write enable signals (e.g., WEH and WEL) to specify and enable a write to one or more bytes of the specified memory location of the Type III external device.
FIG. 3B are typical timing diagrams for I/O signals that are required as input into the external device of FIG. 3A to enable a read operation. As shown, the CS! signal transitions from a high state 308 to a low state 312 to enable access to the Type III external device. Additionally, the RD! signal transitions from a high value 314 to a low value 318 to enable the read operation. The WEH and WEL signals remain at high states 320 and 322 during a read operation.
FIG. 3C are typical timing diagrams for I/O signals that are required as input into the external device of FIG. 3A to enable a write operation. As shown, the I/O signals for a write operation are similar to the I/O signals for a read operation. However, the RD! remains at a high state 364. Additionally, one or both of the write enable signals (e.g., WEL and WEH) transition from a high state (e.g., 366 and 372) to a low state (e.g., 370 and 376) to enable a write operation only to the indicated bytes(s).
FIG. 4A is a diagrammatic representation of an external device 400 of a fourth subtype (Type IV) and associated I/O pins. Siemens' HYB 3164 (5/6)160AT(L)-40/-50/-60 4 M.times.16 DRAM is an example of a Type IV external device, a specification of which is included in Appendix A as Item 4 (incorporated herein by reference in its entirety). As shown, Type IV is configured to receive a plurality of address (ADR) signals, a plurality of data signals (DB), an upper column address strobe (UCAS!) signal, a lower address column strobe (LCAS!) signal, a read (RD!) enable signal, a write (WR!) enable signal, and a row address strobe (RAS!) signal. Some Type IV external devices require only a single CAS! signal, while other Type IV external devices require more than one pair of CAS! signals.
The RAS signal indicates when to read the row address value from the ADR signals, and the UCAS and LCAS indicate when to store the column address from the ADR signals within the external device 400. For example, a falling edge of the RAS! signal indicates when to store the row ADR values within internal registers (not shown) of the external device 400. Likewise, a falling edge of one or both of the CAS! signals indicate when to store the column ADR values within internal registers (not shown) of the external device 400. One or both of the UCAS and LCAS signals may be used to indicate which bytes to read from or write to within the external device 400. The RD! signal is used to enable a read from the external device 400, and the WR! signal is to enable a write to the external device 400.
FIG. 4B are timing diagrams for I/O signals that are typically input into the external device 400 of FIG. 4A during a read operation. As shown, the timing diagrams include address (ADR) signals, a plurality of data signals (DB), an upper column address strobe (UCAS!) signal, a lower address column strobe (LCAS!) signal, a read (RD!) enable signal, a write (WR!) enable signal, and a row address strobe (RAS) signal.
As shown, row address values (e.g., 404) and column address values (e.g., 406) are multiplexed onto the ADR signals. For example, a first row address 404 is received by the external device 400, a first column address 406 is then received, a second row address 410 is then received, etc. The RAS! signal transitions from a high value 412 to a low value 416 to indicate that the row address value may be read by the external device. One or both of the CAS! signals transition from a high value 418 to a low value 422 to indicate that one or both bytes of the column address may be read by the external device. If the UCAS! signal is low, the upper byte of data is read and if the LCAS! signal is low, the lower byte of data is read.
The RD! signal transitions from a high value 424 to a low value 428 to enable a read operation. The WR! signal remains at a high value 430 such that a write operation is not enabled. Alternatively, the Type IV external device may include a combined read and write enable signal, instead of separate read and write enable signals.
FIG. 4C are typical timing diagrams for I/O signals that are required as input into the external device 400 of FIG. 4A to enable a write operation. As shown, the I/O signals for a write operation are similar to the I/O signals for a read operation. However, the WR! signals transitions from a high value 476 to a low value 480 to enable the write operation, and the RD! signal remains at a high state 474.
Although a particular microcontroller typically meets the interfacing requirements for one or two types of external device, conventional microcontrollers are typically not capable of interfacing with more than one type of external device. For example, a microcontroller may be configured to provide separate read and write signals for a Type I external device, but not a combined read and write signal for a Type II external device.
As a consequence of the limited interface capabilities of conventional microcontroller configurations, system designers who desire to couple a single microcontroller unit with more than one type of external device must implement additional hardware (or "glue logic") that is custom designed to provide interface capabilities for more than one type of external device. For example, a microcontroller that is configured to only provide separate read and write signals requires additional glue logic to combine the read and write signals for interfacing with a Type II external device.
In view of the foregoing, there is a need for an improved microcontroller that is capable of interfacing with multiple external devices without the addition of external glue logic.